Content Addressable Memories and Transformable Logic Circuits Based on Ferroelectric Reconfigurable Transistors for In-Memory Computing

As a promising alternative to the Von Neumann architecture, in-memory computing holds the promise of delivering high computing capacity while consuming low power. Content addressable memory (CAM) can implement pattern matching and distance measurement in memory with massive parallelism, making them highly desirable for data-intensive applications. In this paper, we propose and demonstrate a novel 1-transistor-per-bit CAM based on the ferroelectric reconfigurable transistor. By exploiting the switchable polarity of the ferroelectric reconfigurable transistor, XOR/XNOR-like matching operation in CAM can be realized in a single transistor. By eliminating the need for the complementary circuit, these non-volatile CAMs based on reconfigurable transistors can offer a significant improvement in area and energy efficiency compared to conventional CAMs. NAND- and NOR-arrays of CAMs are also demonstrated, which enable multi-bit matching in a single reading operation. In addition, the NOR array of CAM cells effectively measures the Hamming distance between the input query and stored entries. Furthermore, utilizing the switchable polarity of these ferroelectric Schottky barrier transistors, we demonstrate reconfigurable logic gates with NAND/NOR dual functions, whose input-output mapping can be transformed in real-time without changing the layout. These reconfigurable circuits will serve as important building blocks for high-density data-stream processors and reconfigurable Application-Specific Integrated Circuits (r-ASICs). The CAMs and transformable logic gates based on ferroelectric reconfigurable transistors will have broad applications in data-intensive applications from image processing to machine learning and artificial intelligence

Low-Thermal-Budget Ferroelectric Field-Effect Transistors Based on CuInP2S6 and InZnO

In this paper, we demonstrate low-thermal-budget ferroelectric field-effect transistors (FeFETs) based on two-dimensional ferroelectric CuInP2S6 (CIPS) and oxide semiconductor InZnO (IZO). The CIPS/IZO FeFETs exhibit non-volatile memory windows of ~1 V, low off-state drain currents, and high carrier mobilities. The ferroelectric CIPS layer serves a dual purpose by providing electrostatic doping in IZO and acting as a passivation layer for the IZO channel. We also investigate the CIPS/IZO FeFETs as artificial synaptic devices for neural networks. The CIPS/IZO synapse demonstrates a sizeable dynamic ratio (125) and maintains stable multi-level states. Neural networks based on CIPS/IZO FeFETs achieve an accuracy rate of over 80% in recognizing MNIST handwritten digits. These ferroelectric transistors can be vertically stacked on silicon CMOS with a low thermal budget, offering broad applications in CMOS+X technologies and energy-efficient 3D neural networks

Ferroelectric doped hafnium oxide and its application on electronic devices

Ferroelectricity is the material property such that we can induce spontaneous polarization, reverse it and modulate it by varying the applied electrical field on the ferroelectric material. Recently, doped hafnium oxide (HfO2) has garnered attention with its excellent scalability, reliability, and compatibility with the current CMOS process. This thesis introduces two research projects aimed at improving the electrical properties of ferroelectric-doped HfO2 for various device applications. In the first project, we demonstrate a high-performance ferroelectric aluminum (Al) doped HfO2 capacitor with Ti/Pd gate electrode. The remnant polarization reaches up to 20 µC/cm2, endurance higher than 10^8 cycles and retention over ten years at room temperature. In the second research, we demonstrate a ferroelectric tunneling junction (FTJ) based on metal/aluminum oxide/zirconium doped HfO2/silicon structure. We show that this FTJ has artificial synaptic behavior with symmetric synaptic weight change and tunable conductance. We also show spike-timing-independent plasticity (STDP) can be obtained in this device, which proves the possibility of using our FTJ as a neuromorphic computing chip

Bridging TCAD and AI: Its Application to Semiconductor Design

There is a growing consensus that the physics-based model needs to be coupled with machine learning (ML) model relying on data or vice versa in order to fully exploit their combined strengths to address scientific or engineering problems that cannot be solved separately. We propose several methodologies of bridging technology computer-aided design (TCAD) simulation and artificial intelligence (AI) with its application to the tasks for which traditional TCAD faces challenges in terms of simulation runtime, coverage, and so on. AI-emulator that learns fine-grained information from rigorous TCAD enables simulation of process technologies and device in real-time as well as large-scale simulation such as full-pattern analysis of stress without high demand on computational resource. To accelerate atomistic molecular dynamics (MD) simulation, we have done a comparison study of descriptor-based and graph-based neural net potential, and also show their capability with large-scale and long-time simulation of silicon oxidation. Finally, we discuss the use of hybrid modeling of AI- and physics-based model for the case where physical equations are either fully or partially unknown